Chair News

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The chair for compiler construction contributed with a demonstration to the IEEE 5G Summit Dresden, held at the International Congress Center on the 25th of September. Robert Khasanov together with Till Smejkal from the Chair of Operating Systems demonstrated recent research results on compiler-assisted run-time adaptivity, an integral part of the HAEC collaborative research center. The demonstration builds on previously published works, mainly work on general symmetries in hardware and their application to software mapping at runtime. 

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The chair for compiler construction was represented by Andres Goens during a special session on “scalable and flexible manycore mapping techniques ” at the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-18) in Hanoi, Vietnam. The session also included talks from Takashi Abe (DENSO, Japan),  Anuj Pathania (with Prof. Tulika Mitra at NUS, Singapore) and Tobias Schwarzer (with Prof. Jürgen Teich at FAU, Germany).  Andres presented his work “On the Representation of Mappings to Multicores”, which argued for abstractly studying the mathematical representations of mappings for different research questions. 

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We are happy to host Joonas Multanen as visiting PhD researcher for the next four months. Joonas received his M.Sc.degree in Electrical Engineering from Tampere University of Technology (TUT) in 2015. He is currently a graduate student at the Laboratory of Pervasive Computing in TUT. His research interests include energy efficient computer architectures, emerging memory technologies and computer graphics. Joonas will give a talk on  "Instruction Stream Energy Optimization”, describing his PhD research work. Previously, Joonas has worked to improve the energy-efficiency of instruction streams in processors, with the goal being fixed-function accelerator energy-efficiency, but with the flexibility brought by programmability. The research visit aims to apply emerging memory technologies to processor instruction streams and to develop techniques to improve their performance and energy-efficiency when used as instruction storages.

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On the 28th of June, Prof. Castrillon gave an invited talk at the "Post Moore Interconnects Workshop" co-located with the ISC high performance conference in Frankfurt, Germany. This event, organized by Dr. Neena Imam from the Oak Ridge National Laboratory in the US, gathered together experts from technology, system architecture and system's software to talk about upcoming technologies with a strong emphasis on interconnects. Prof. Castrillon shared the vision of the Orchestration Path of cfaed (slides).   

 

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Prof. Castrillon was invited to give an opening talk at the 50-year Celebration of the Department of Electronics, Universidad de Antioquia (UdeA, in the context of the IEEE Colombian Conference on Communications and Computing (COLCOM). On May 16, Prof. Castrillon talked about the why of parallel programming as well as dataflow-based programming models and domain specific languages for today’s and future computing systems (see here). He also participated in a discussion panel about the role of research at the Universidad de Antioquia. 

 

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The chair for compiler construction just moved to the new cfaed building. We left our old address at Georg-Schumann-Str. 7A and are now to be found at 

Building Barkhausenbau 
Helmholtzstrasse 18
3rd floor, rooms BAR III50 – III82
01069 Dresden
Germany

While still under construction, it is not easy to find the way. Look at our contact page for detailed directions. 

 

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Norman and Sebastian gave 3 talks at this years CC-CGO-PPoPP-HPCA Joint Conference series:

In the workshop for Real World DSLs (RWDSL), Norman presented his work on a DSL for computational fluid dynamics. At the Compiler Construction (CC) conference, Sebastian gave a talk on our compiler framework Ÿauhau that optimizes I/O in microservices. Finally, Sebastian presented work on implicit parallel programming in the domain of big data systems in a workshop on Programming Models and Applications for Multicores and Manycores (PMAM). All talks were well received and inspired interesting discussions.

 

The Chair for Compiler Construction was well-represented at this year's HiPEAC conference

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The Chair for Compiler Construction was well represented at the HiPEAC Conference, which took place in Manchester, UK from January 22nd-24th 2018. The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems. Three researchers from the chair presented their work in the main-track session and co-located workshops. Andrés Goens presented his papers “Symmetry in Software Synthesis” in the main track session and “Level Graphs: Generating Benchmarks for Concurrency Optimizations in Compilers” in the co-located workshop MULTIPROG’18. Robert Khasanov presented his paper “Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap” in the workshop PARMA-DITAM and Asif Ali Khan presented his paper “NVMain Extension for Multi-Level Cache Systems” in the RAPIDO workshop. The three researchers participated in the social event and other conference sessions where they met like-minded individuals from across the globe and discussed the general perspective of their research areas.

 

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Last week, the IEEE Rebooting Computing 2017 Industry Summit on the Future of Computing was held in Washington, DC. The cfaed Strategic Professor for Compiler Construction Jeronimo Castrillon was invited for a talk within the Innovation and Ideas Panel. See his presentation as well as the talks of Bing Liu (University of Illinois at Chicago), Robert Voigt (Northrop Grumman Corporation), and Dario Gil (IBM Research) which are followed by a panel discussion.
cfaed supported "Rebooting Computing Week 2017" as a Silver Patron.

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The chair for compiler construction presented a paper at the MEMSYS Conference, from October 2nd to 5th, 2017. MEMSYS is a unique conference dealing with memory technologies. This conference provides an excellent discussion platform for researchers from cross-disciplinary domains including people from the application, operating system, compiler, system architecture, interconnect, and circuits domains. Fazal Hameed presented his paper at the conference “Efficient STT-RAM Last-Level-Cache Architecture to replace DRAM Cache” in a session that discussed cache architecture and management.